Publications Repository - Helmholtz-Zentrum Dresden-Rossendorf

Material behavior and properties at different scales, from nanometers to millimeters, are the input data needed for a model-based design-for-manufacturing approach of 3-D through-silicon-via (TSV) stacked ICs. In particular, mechanical and thermomechanical material data have to be used as input for physics-based modeling and simulation of stress-induced phenomena in 3-D stacks. Both package-and wafer-level properties, including their interaction, have to be considered. This paper reviews the thermomechanical and mechanical properties of several structures: time-dependent properties of solder materials (millimeter and micrometer scales), microstructure-dependent properties of Cu TSVs (micrometer scale), and process-dependent properties of ultralow-k materials in on-chip interconnect stacks (10-nm scale). To minimize the keep-out zone for active devices in the stress-affected surrounding of TSVs, while maintaining the device performance during 3-D TSV stacking of ICs, highly accurate material data are needed as input for the thermomechanical stress simulation. A similar strategy is supposed to be developed for a model-based design-for-reliability approach of 3-D TSV stacked ICs.