Apollo VP2/97

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Product Description Press Coverage
Key Features News Releases
Block Diagram Chipset Comparison Guide
Datasheets Purchase
Performance Results


VT82C590 Apollo VP2/97
The two chip Apollo VP2/97 is the industry’s most highly integrated, high-performance and fully compatible Socket-7 chipset. With ECC, Microsoft® PC97 compliance, SDRAM, 512MB DRAM and 2MB cache the VP2/97 is the only chipset in its class to incorporate the industry’s complete set of leading-edge technologies. This product offers a new level of flexibility, scalability, performance and data transmission integrity. Recognizing its leading-edge design, AMD recently licensed the VIA Apollo VP2/97 core logic architecture as its AMD 640 chipset.

Compatibility
VIA is working to provide the highest level of technology integration for the Socket-7 mainboard infrastructure. The VIA Apollo VP2/97 is the optimal choice for the full range of Socket-7 processors and cache interfaces, including, Intel Pentium®, and Pentium® processor with MMXTM, Cyrix/IBM 6x86TM and 6x86MXTM, and AMD K5 and K6 MMXTM.

PC97 Compliant
The VIA Apollo VP2/97 features the VIA VT82C586B PCI-IDE south bridge controller chip. Highly integrated, this chip complies with the Microsoft® PC97 industry specification by supporting ACPI/OnNow, Ultra DMA/33 and USB technologies.

Performance
The Apollo VP2/97 builds on the legacy of the VIA VT82C580VP
Apollo VP, widely recognized by leading international IT publications as the highest performing Socket-7 chipset. Key performance enabling features include support for up to 2MB of L2 cache and up to 512MB DRAM. Additonal performance related features include a fast DRAM controller with support for SDRAM, EDO, BEDO and FPM DRAM types in mixed combinations with 32/64 bit data bus widths and row and column addressing, a deeper buffer with enhanced performance, an intelligent PCI bus controller with Concurrent PCI master/CPU/IDE operations and zero-wait-state PCI master and slave burst transfer rates.

Reliability
For server support and data integrity, the VP2/97 incorporates Error Checking and Correcting (ECC).


KEY FEATURES:

ECC
PC97 compliance
Extension to ACPI/OnNow
Universal Serial Bus Controller
Enhanced Master Mode PCI IDE Controller with extension to Ultra DMA/33
Support for up to 512MB DRAM
DRAM controller with fast page mode/EDO/Synchronous DRAM support in mixed combinations with 32 bit or 64 bit data bus widths and row and column addressing
Deeper buffer with enhanced performance
Intelligent PCI bus controller offering concurrent PCI master/CPU/IDE operations and zero wait state PCI master and slave burst transfer rates
Integrated Keyboard Controller and Real-Time Clock
Flexible CPU Interface with support for Pentium®, and Pentium®, processor with MMX(tm), Cyrix 6x86(tm) and M2, and AMD K5 and K6 MMX(tm)
Advanced Cache Controller with burst synchronous cache SRAM support up to 2MB
Plug and Play Controller
PCI to ISA Bridge
Built-in nand-tree pin scan test capability
0.6um mixed voltage, high speed and low power CMOS process
328 pin BGA Package for VT82C595 north bridge controller chip
208 pin PQFP for VT82C586B south bridge controller chip



Performance Results
Block Diagram
Datasheets
These files require Adobe® Acrobat®.
VT82C595 Datasheet
VT82C586B Datasheet
Chipset Comparison Guide
Compare VP2/97 features with other PCIsets on our Chipset Comparison Guide
News Releases
07/21/97 "Apollo VP2 Is Performance Leader"
03/11/97 "VIA Licenses Its VP2/97 Core Logic Design to AMD"
05/13/96 "VIA Rolls Second Generation P54C Core Logic Chip Set"
Read All About It
Have a look at what the press is saying.
Purchase Information
Please see our
Purchase Page for more information.

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